Wideband Darlington amplifiers with high linearity are standard radio frequency (RF) building blocks for wireless, cable television (CATV), fiber optics, and general purpose RF applications. An important attribute for such applications are high linearity over multi-decade bandwidth operation. One figure of merit for weakly nonlinear systems such as small signal RF amplifiers is known as a third order intercept point (IP3). A relatively high value for IP3 measured in decibels referenced to one milliwatt (dBm) indicates a relatively high linearity for a device or system, whereas a relatively low value for IP3 indicates a relatively low linearity for a device or system. A low linearity for an RF device such as an amplifier or mixer will cause inter-modulation (IM) products to be generated that cannot be filtered out before reaching a receiver.
Darlington amplifiers based upon Indium Gallium Phosphide (InGaP) heterojunction bipolar transistors (HBTs) have demonstrated some of the highest IP3-bandwidth (IP3-BW) values for an RF Darlington feedback amplifier. FIG. 1 is a circuit diagram of a simple embodiment of a prior art self-biased Darlington feedback topology. In particular, the self-biased Darlington feedback amplifier 10 depicted in FIG. 1 includes features disclosed in U.S. Pat. No. 6,972,630 and U.S. Pat. No. 6,927,634, both of which are entitled “Self-Biased Darlington Amplifier”, both of which are incorporated herein by reference in their entirety. Moreover, the self-biased Darlington feedback amplifier 10 has been implemented using Silicon Germanium (SiGe) and Indium Gallium Phosphide (InGaP) heterojunction bipolar transistor technologies as well as enhancement mode (E-mode) pseudomorphic high electron mobility transistor (PHEMT) technology. Robust operation over temperature and process variation is a key advantage of the self-biased Darlington feedback amplifier 10. Moreover, the self-biased Darlington feedback amplifier 10 eliminates the need for an off-chip active bias network such as a positive-negative-positive (PNP) transistor network. Further still, the self-biased Darlington feedback amplifier 10 provides inherent benefits of an intermediate frequency (IF) or beat tone cancellation through negative feedback. The self-biased Darlington feedback amplifier 10 also includes a unique ability of enabling class B biasing, which is not possible with traditional Darlington feedback amplifiers that use a resistive bias network that restrict traditional Darlington amplifiers to class A operation.
In particular, the self-biased Darlington feedback amplifier 10 illustrates a basic embodiment prior art self-biased Darlington feedback topology. A main amplifier section 12 may be implemented with a transistor Q1 and a transistor Q2. A bias section (or circuit) 14 is generally connected between the emitter and base of the transistor Q1. The bias section 14 is implemented as a self-biased feedback circuit. The self-biased Darlington feedback amplifier 10 also comprises a parallel feedback resistor RFB, a series feedback resistor REE2, and a bias resistor REE1. The bias resistor REE1 is used to bias the transistor Q1. The bias section 14 is used to stabilize the bias of the self-biased Darlington feedback amplifier 10 without relying on an external resistor.
The self-biased feedback circuit 14 generally comprises a blocking resistor RDC, a transistor QBIAS, a resistor RISO, a resistor REEBIAS and a bypass capacitor CBYP1. The resistor RDC is implemented as an RF blocking resistor. The transistor QBIAS is implemented as a biasing transistor. The resistor RISO is implemented as an RF isolation for preventing RF or intermediate frequency IF signals from being fed back to the base of transistor Q1. The emitter biasing resistor REEBIAS may be coupled between the emitter of the transistor QBIAS and a fixed voltage node such as ground. The capacitor CBYP1 is implemented as an alternating current (AC) bypass capacitor. The transistor QBIAS generally operates as a pseudo mirror bias transistor of the transistor Q2. The bias section 14 generally works in conjunction with the parallel feedback resistor RFB to set up a reference current IBB. The reference current IBB is approximately mirrored to the transistor Q2 as a bias current ICC2. The relationship between IBB and ICC2 is only approximate, but generally mirror each other in current over temperature, supply voltage, and input drive level variations. The ratio of the areas of the transistor QBIAS and the transistor Q2, and the emitter resistors REEBIAS and REE2, are generally scaled in proportion to the bias currents IBB and ICC2, respectively. For example, if the bias current IBB is 1 mA and the bias current ICC2 is 100 mA, then the area of the transistor QBIAS may be implemented as 1/100th of the area of the transistor Q2. The resistor REEBIAS will approximately be one hundred times the value of the resistor REE2. However, other ratios may be implemented to meet the design criteria of a particular implementation.
The values of the blocking resistor RDC and the resistor RISO are generally chosen for optimum RF performance versus DC bias sensitivity. For optimal RF performance, the resistor RISO should typically be greater than about 10Ω but less than about 1,000Ω. The value of the blocking resistor RDC should typically be greater than about 100Ω but less than about 10,000Ω. DC stability may be relaxed in favor of RF performance or vice versa to obtain combinations outside of these ranges.
The bypass capacitor CBYP1 and the blocking resistor RDC set a lower frequency limit of operation. The lower frequency limit of operation may be extended by increasing either or both values of the capacitor CBYP1 and the blocking resistor RDC. However, increasing the value of the resistance of the blocking resistor RDC will generally degrade the bias mirroring relationship between the transistor QBIAS and the transistor Q2. The self-biased Darlington feedback amplifier 10 resembles a type of DC current mirror, except that the self-biased Darlington feedback amplifier 10 provides a well defined RF input terminal IN and a well defined RF output terminal OUT. The DC mirror operation is less than ideal due to the RF blocking resistor RDC.
FIG. 2 shows a prior art E-mode PHEMT implementation of the self-biased Darlington feedback amplifier 10 (FIG. 1). A field effect transistor (FET) based self-biased Darlington feedback amplifier 16 includes transistors M1, M2 and M3. E-mode PHEMT devices are chosen for the transistors M1, M2 and M3 because a positive gate to source threshold voltage VGS of E-mode PHEMT devices enables positive supply operation of self-biased Darlington feedback amplifiers. In contrast, depletion mode (D-mode) PHEMT devices are not usable for the transistors M1, M2, and M3, because D-mode devices do not work properly with the FET based self-biased Darlington feedback amplifier 16. Moreover, enhancement mode (E-mode) PHEMT FETs have low parasitic characteristics that allow greater IP3-BW performance as compared to traditional SiGe and InGaP HBT Darlington RF feedback amplifiers. For example, FIG. 3 illustrates a significantly flat response for IP3 over a wideband of frequencies for E-mode PHEMT based Darlington amplifiers, whereas InGaP HBT Darlington amplifiers experience a relatively sharp roll-off over the same wideband frequencies, given a similar bias voltage and current operation.
Turning back to FIG. 2, the transistors M1, M2, and M3 are FET devices that have an order of magnitude lower input capacitance CGS in comparison to a bipolar or HBT device for a similar bias current level. A smaller set of parasitic capacitances help preserve a desirable 180 degree negative feedback at an upper edge of the wideband frequencies of operation. A non-ideal feedback that is less than or greater than 180 degrees at the upper edge of the wideband frequencies of operation will yield a vector feedback that departs from the desirable 180 degree negative feedback. This less than desirable negative feedback is a result of excessive parasitic device capacitance that produces feedback signal phase shifts that result in less than desirable negative feedback distortion cancellation.
In greater detail, the FET based self-biased Darlington feedback amplifier 16 includes a main amplifier section 18 that is implemented with the transistor M1 and transistor M2. A FET bias section 20 is communicatively coupled between the drain of the transistor M1 and gate of the transistor M2. The FET bias section 20 is implemented as a self-biased feedback circuit. The FET based self-biased Darlington feedback amplifier 16 also comprises the parallel feedback resistor RFB, a series feedback resistor RSS2, and a bias resistor RSS1. The bias resistor RSS1 is used to bias the transistor M1. The FET bias section 20 is used to stabilize the bias of the FET based self-biased Darlington feedback amplifier 16 without relying on an external resistor. A resistor RGM serves the function of RDC (FIG. 1) and a capacitor CG serves the function of CGYP1 (FIG. 1). A capacitor CBYPASS coupled between a power supply rail VDD and ground GND filters power that supplies the FET based self-biased Darlington feedback amplifier 16. An inductor LCHOKE prevents RF signals that are amplified by the FET based self-biased Darlington feedback amplifier 16 from passing to GND through either VDD or the capacitor CBYPASS.
FIG. 4 depicts a prior art linearized Darlington cascode amplifier 22 for addressing the non-ideal phase due to parasitic capacitances and parasitic inductances. In particular, the linearized Darlington cascode amplifier 22 generally comprises an amplifier section 24, a reference voltage generation circuit 26, and resistors RFB, RBB, RE1, and RE2. The amplifier section 24 generally comprises a transistor Q1, and a transistor Q2. The resistor RFB is a parallel feedback resistor. The resistor RE2 is a series feedback resistor. The resistors RE1 and RBB are bias resistors.
A transistor Q3 is a common base transistor. The transistor Q3 generally acts to increase the breakdown voltage and bandwidth of the amplifier section 24 and also compensates for an open-loop insertion phase of the amplifier section 24, which is dependent on the impedance characteristic of the reference voltage generation circuit 26 coupled to the base of the transistor Q3.
The reference voltage generation circuit 26 is a frequency dependent voltage reference circuit. The reference voltage generation circuit 26 may include an emitter follower (not shown), and at least one inductive element (not shown). The inductive element helps to provide a desirable frequency dependent impedance to the base of the common-base transistor Q3. Further elements can be added to the inductive element to construct a resistor-inductor-capacitor (RLC) network for optimizing gain-bandwidth, IP3, and/or stability performance. By choosing an appropriate combination of the RLC network, the broadband impedance of the reference voltage generation circuit 26 may be tailored to create an optimal impedance and phase at the collector of the transistor Q3, which generally results in improved broadband IP3 performance.
FIG. 5 is a graph that provides an IP3 comparison between a conventional Darlington amplifier (not shown) and the linearized Darlington cascode amplifier 22 (FIG. 4). In comparison to a conventional Darlington amplifier, the linearized Darlington cascode amplifier 22 provides higher IP3 values from about 2G Hz out to about 16 GHz. In the particular example of FIG. 5, a maximized IP3 improvement value is about 7 dBm at about 12 GHz. Overall, the measured IP3 data shows about an 80% improvement in IP3-BW product.